High Performance Superconducting Qubit Systems (HiPS)

Eligibility: 

Eligible applicants under this BAA include Institutions of higher education (foreign and domestic), nonprofit organizations, and for profit concerns (large and small businesses). 

Contact: 

Grantor Contact Information: If you have difficulty accessing the full announcement electronically, please contact Andrew Day

Website

Deadline Details: 

White paper: Sponsor deadline - No, but strongly suggested, 07 Aug 2017 4:00 PM Eastern Daylight Savings Time

Proposals: Sponsor deadline - required, 18 Sep 2017 4:00 PM Eastern Daylight Savings Time

The U.S. Army Research Office (ARO) in collaboration with the National Security Agency (NSA) is soliciting proposals for research in High Performance Superconducting Qubit Systems. This BAA has two primary goals;

(a) substantially improve the fidelity of one and two-qubit operations over current state-of-the-art performance, and

(b) design and test qubits with built-in error protection.

While proposals that advance both primary goals in an integrated approach are encouraged, proposers may focus on either goal individually, given the state-of-the-art of their approach. There are two types of proposals with different research scopes covered in this announcement: 1. High performance superconducting qubit systems a. High Fidelity 2-qubit gates b. Error protected qubits 2. Key supporting technology to high-performance superconducting qubits

Option 1: High performance superconducting qubit systems

Option 1a: Proposals are sought from integrated multi-disciplinary teams fully capable of addressing all the necessary challenges towards implementing high fidelity 2-qubit gates. A strength of the superconducting approach to quantum computing is that qubits are easily coupled to one another and in many ways using various combinations of capacitors, inductors, Josephson Junctions, and resonators. As a result, many different two-qubit gate protocols have been developed over the past few years, with gate errors now approaching the 10-2 to 10-3 range. While improving the 2- qubit gate fidelity is the primary goal of this option, it should be achieved without sacrificing one-qubit gate error, state preparation and measurement errors, along with the other identified device metrics.
The first primary goal in option 1a focuses on reducing the 2-qubit gate error. Submissions must clearly motivate the proposed approach the team wishes to pursue, current state-of-the-art performance levels, key challenges that need solving, anticipated sources of error and quantitative descriptions of predicted improved 2-qubit gate performance.
Required End-of-Program demonstrations for high-fidelity qubit operations:

  1. A device with four or more qubits with individual qubit control and readout
  2. One and two-qubit gate errors ≤ 10-3
  3. Readout fidelities ≥ 99% in < 500 ns

Sufficient characterization and control of these low two-qubit gate error rates relies on continued improvement and simplification of control and measurement technologies such as electronics capable of fast feedback and control, and simplified quantum noise limited measurement chains. Gate fidelity must be confirmed using community standard characterization techniques such as randomized benchmarking or gate-set-tomography or similar routines and all sources of noise must be carefully identified, quantified and compared with theory/expectations.

Option 1b: The second primary goal of this BAA focuses on improving qubit coherence using noise protected few qubit designs. The coherence of superconducting qubits has steadily increased over time, starting with the initial measurements published in 1999 and increasing at a rate of almost an order of magnitude every three years. A key factor contributing to this success is the development of qubits that are less sensitive to typical noise sources. For example, the Cooper- Pair-Box underwent many re-designs over the years, eventually transforming into the transmon qubit that has vastly reduced sensitivity to charge noise. However, transmons are still sensitive to surface losses and, if tunable, flux noise. To continue these advances in coherence an example approach may be developing qubits with inherent error protection in the form of new superconducting qubit designs and/or novel encodings which are more immune to noise.
Submissions must clearly motivate the proposed approach the team wishes to pursue, current state-of-the-art coherence levels, key noise sources that need mitigating and quantitative descriptions of predicted improved coherence (T2) performance for the proposed approach.
Required End-of-Program demonstrations:

  1. Substantial improvement in coherence (T2) over state-of-the-art conventional approach
  2. Demo of 1 and 2-qubit gate errors ≤ 10-2
  3. Practical path to scaling to a 10-qubit device with sufficient 2-qubit gate connectivity to run a performer-specified algorithm of interest e.g. error correction

Proposals addressing both primary goals 1a and 1b should appropriately combine both sets of end-of-program demonstrations. Proposals should also clearly identify intermediate annual milestones that measure progress towards the required end-of-program demonstrations. The proposed team must have all the needed capabilities and expertise to execute their proposed research plan e.g. theoretical support, optimal control, microwave circuit design, fabrication, cryogenic and microwave control, low-noise readout and high fidelity quantum characterization. The team may leverage anticipated research achievements from projects funded within the team by other sources. Such dependencies must be clearly identified.

Option 2: Contributions to high-performance superconducting qubit systems

Innovative proposals are sought for narrowly scoped efforts to identify and address current key supporting technologies needed to remove barriers to significantly improve the performance of superconducting qubit systems. Examples of key supporting technologies could be low loss superconducting cryogenic microwave devices, integrated quantum limited readout circuitry, modeling tools, fabrication techniques, or simplified control electronics with fast feedback capabilities. Proposals must clearly identify the chosen supporting technologies, the barrier removed, and the research approach and challenges to overcoming the barrier. Proposals should place the technology in the appropriate context: discuss both the current state of the art, and the impact of improving this technology. Annual intermediate milestones and end-of-program demonstrations must be provided, including a final demonstration utilizing the supporting technology for its intended application. Experimental validation that the technology aids or improves gate performance as predicted is desirable. Addressing multiple key supporting technologies in a single proposal must be strongly motivated by a unifying research goal. Proposals that simply aim to demonstrate a subset of Options 1 goals are discouraged.