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Alex Jones

University of Pittsburgh
Ph.D., Electrical and Computer Engineering, Northwestern University, 2002; M.Sc., Computer-aided design and Parallel FPGA design, Northwestern University, 2000; B.Sc., Physics, The College of William and Mary, 1998

Alex K. Jones is a Professor of Electrical and Computer Engineering and Computer Science (by courtesy) at the University of Pittsburgh.  He is currently on leave from Pitt to serve as a Program Director in the CNS Division of CISE at the US NSF. 


Dr. Jones’ research interests are broadly in the area of computer architecture.  He is currently investigating quantum system codesign including design of basis gates, topologies, and transpilation from resonator devices to systems.  He is also actively developing nanoscale magnetic memory systems including spin-transfer-torque and Racetrack memories with an emphasis on processing in memory.  His other interests include reliability and fault-tolerance, computing and memories in harsh environments such as space, compilation techniques for configurable systems and architectures, and sustainable computing, among others.  He has more than 200 publications in these areas.  His research is funded by NSF, DARPA, NSA, and industry.


Title Position Email
Quincy Bayer Undergraduate Student
Preston Brazzle Graduate Student
Ryan Caginalp Undergraduate Student
Stephen Cahoon Graduate Student
Evan McKinney Graduate Student
Sebastien Ollivier Postdoctoral Fellow
Most Cited Publications

K.J. Barker; A. Benner; R. Hoare; A. Hoisie; A.K. Jones; D.K. Kerbyson; D. Li; R. Melhem; R. Rajamony; E. Schenfeld; S. Shao; C. Stunkel, P. Walker, "On the Feasibility of Optical Circuit Switching for High Performance Computing Systems," SC '05: Proceedings of the 2005 ACM/IEEE Conference on Supercomputing, 2005, pp. 16-16, doi: 10.1109/SC.2005.48.
Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, and John Foster. 2005. An FPGA-based VLIW processor with custom hardware execution. In Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05). Association for Computing Machinery, New York, NY, USA, 107–117.
Y. Zhang, X. Wang, Y. Li, A. K. Jones and Y. Chen, "Asymmetry of MTJ switching and its implication to STT-RAM designs," 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1313-1318, doi: 10.1109/DATE.2012.6176695.
Yong Li, Ahmed Abousamra, Rami Melhem, and Alex K. Jones. 2010. Compiler-assisted data distribution for chip multiprocessors. In Proceedings of the 19th international conference on Parallel architectures and compilation techniques (PACT '10). Association for Computing Machinery, New York, NY, USA, 501–512.
S. M. Seyedzadeh, A. K. Jones and R. Melhem, "Counter-Based Tree Structure for Row Hammering Mitigation in DRAM," in IEEE Computer Architecture Letters, vol. 16, no. 1, pp. 18-21, 1 Jan.-June 2017, doi: 10.1109/LCA.2016.2614497.

Recent Publications

Evan McKinney, Mingkang Xia, Chao Zhou, Pinlei Lu, Michael Hatridge, Alex K Jones, “Co-Designed Architectures for Modular Superconducting Quantum Computers,” arXiv preprint arXiv:2205.04387, 2022, doi: 10.48550/arXiv.2205.04387

S. Ollivier, X. Zhang, Y. Tang, C. Choudhuri, J. Hu and A. K. Jones, "POD-RACING: Bulk-Bitwise to Floating-Point Compute in Racetrack Memory for Machine Learning At the Edge," in IEEE Micro, 2022, doi: 10.1109/MM.2022.3195761

S. Ollivier, S. Longofono, P. Dutta, J. Hu, S. Bhanja and A. K. Jones, "Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories with PIETT," in IEEE Transactions on Computers, 2022, doi: 10.1109/TC.2022.3188206.

S. Longofono, S. M. Seyedzadeh and A. K. Jones, "Virtual Coset Coding for Encrypted Non-Volatile Memories with Multi-Level Cells," in Proc. of the 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, pp. 1128-1140, doi: 10.1109/HPCA53966.2022.00086

Sebastien Ollivier, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, and Alex K. Jones, “CORUSCANT: Processing-in-Racetrack Memories,” in Proc. of the IEEE/ACM Symposium on Microarchitecture (MICRO), 2022.